The subject system and method are generally directed to optimizing the electrical integrity analysis of an electronic system to be implemented (be it on a chip, package, or board level). The system and method provide for automated measures to ensure that various electrical integrity analyses in a simulated environment, such as for signal integrity, accurately and efficiently account for flight time skew of timing signals that the electronic system would actually encounter (and suitably account for) when physically implemented. The system and method provide such measures which automatically model the real world operating conditions due to geometry and other factors and more accurately reflect the timing of signals in the physical implementation.
With the ongoing trend of electronic systems implementations growing in sophistication and complexity, it is increasingly important to employ highly accurate and efficient simulation techniques to characterize performance baselines of electronic system designs prior to actual fabrication. Simulation-based analyses, such as Signal Integrity (SI) analyses, are ways to establish the baseline performance of electronic system designs before expending valuable resources in prototyping the same.
These analyses are carried out using suitable simulation and analysis tools. In the case of SI analysis, the analysis is carried out using simplified simulation runs based on behavioral models, rather than on actual transistor or other such hardware models. The benefits of this—in terms of streamlined simulation runs, and the faster analyses and reduced design cycles they permit—are considerable given that a typical electronic circuit board design may contain thousands of nets or more. While simulation runs based on actual transistor models would provide more extensive information about all that is occurring in the modeled hardware, the processing loads and execution times required for the runs would be prohibitive for many applications. Moreover, since SI analysis focuses primarily on signal quality (strengths, speed, fidelity, and the like), the added information would hardly enhance SI analysis enough to justify the additional processing and time costs.
Among the tradeoffs of such streamlined simulation, however, is that certain non-trivial effects are not adequately considered, at least not in sufficiently automated manner. Effects like flight time skew manifest in physical implementations are not intrinsically accounted for in behavioral model based SI topologies employed to represent the given electronic system (or portion thereof). It is normally left to a designer to account for these effects, by either calculating them manually or deriving them through other external means. The timing adjustments which result must then be entered in the simulation and analysis tool if the analytic simulation runs on the SI topologies are to be properly configured.
Such manual calculation means require the user to analyze the nets, then identify and actuate simulation of the required nets (i.e., the clock and its associated strobes) to model read/write leveling. The generated waveforms must then be post processed to calculate the flight time skews and calculate the appropriate timing signal offsets to properly align the associated waveforms during simulation of the read and write cycles. This manual process is not only cumbersome and highly prone to error, it is quite time consuming. The practical effect of this is added complication and delay to the design cycle.
There is therefore a need for a system and method which automatically generates the timing adjustments necessary for accurate simulation of the electronic system portion(s) being analyzed. There is a need for an automated approach whereby such effects as flight time skew in timing signals may be properly accounted for in a behavioral model based simulation environment.